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programmable dual - axis inclinometer/accelerometer data sheet ADIS16201 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2006 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features dual - axis inclinometer/accelerometer measurements 12- , 14 - bit digital inclination/acceleration sensor outputs 1.7 g accelerometer measurement range 9 0 inclinometer measurement range , linear output 1 2 - bit digital temperature sensor output digita lly controlled sensitivity and bias calibration digitally controlled sample rate digitally controlled frequency response dual alarm settings with rate/threshold limits auxiliary digital i/o digitally activated self test digitally activated low power mode spi ? - compatible s erial interface auxiliary 12 - bit adc input and dac output s ingle - supply operation : 3.0 v to + 3.6 v 3500 g powered shock survivability applications platform control, stabilization , and leveling tilt s ensing, i nclinometers motion/ p osition m easurement monitor/a larm d evices ( s ecurity, m edical, s afety) functional block dia gram sclk din dout cs rst dio0 dio1 spi port temperature sensor self-test power management auxiliary i/o alarms digital control signal conditioning and conversion calibration and digital processing ADIS16201 vdd com aux adc aux dac vref dual-axis accelerometer 05462-001 figure 1. g eneral description the ADIS16201 is a complete, dual - axis acceler ation and inclination angle measurement system available in a s ingle compact package enabled by the analog devices i sensor ? integration. by enhanc ing the analog devices i mems ? sensor technology with a n e mbedded signal processing solution, the ADIS16201 provides factory calibrat ed and tunable digital sensor data in a c onvenient format that can be accessed using a serial peripheral interface (spi) . the spi interface provides access to measurements for dual - axis linear acceleration, dual - axis linear inclination angle, temperature, power supply , and one auxiliary analog in put. easy access to calibrated digital sensor data provides developers with a system - ready device, reducing development time, cost , and program risk. unique characteristics of the end system are accommodated easily through several built - in features, such a s a sing le command in - system offset calibration, along with convenient sample rate and bandwidth control. the ADIS16201 offers the following embedded features, which eliminate the need for external circuitry and provide a simplifie d system interface: ? confi gurable alarm function ? auxiliary 12 - bit adc ? auxiliary 12 - bit dac ? configurable digital i/o port ? digital self - test function the ADIS16201 offers two power management features for managing system - level power dissipation: low power mode and a configurable shut down feature. the ADIS16201 is available in a 9.2 mm 9.2 mm 3.9 mm laminate - based land g rid a rray (lga) package with a temperature range of ? 40c to +125c.
ADIS16201 data sheet rev. c | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functi onal block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 sp ecifications ..................................................................................... 3 timing specifications .................................................................. 5 timing diagrams .......................................................................... 5 absolut e maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 13 accelerometer operation .......................................................... 13 inclinometer operation ............................................................. 13 temperature sensor ................................................................... 14 basic operation ............................................................................... 15 data output register access ..................................................... 15 programming and control ............................................................ 17 control register overview ........................................................ 17 control register access ............................................................. 17 control register details ................................................................. 19 calibra tion ................................................................................... 19 calibration register definitions .............................................. 19 alarms .......................................................................................... 21 sample per iod control .............................................................. 23 filtering control ......................................................................... 24 power - down control ................................................................ 24 status feedback ........................................................................... 25 command control ..................................................................... 25 miscellaneous control register ................................................ 26 peripherals ....................................................................................... 27 auxiliary adc function ........................................................... 27 auxiliary dac function ........................................................... 27 general purpose i/o control ................................................... 28 applications ..................................................................................... 29 serial peripheral interface (spi) ............................................... 29 hardware considerations ......................................................... 29 grounding and board layout recomendations .................... 29 bandgap reference ..................................................................... 30 power - on reset operation ....................................................... 30 second - level assembly ............................................................. 30 example pad layout ................................................................... 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 r evision history 8 / 13 rev. b to rev. c changes to en dnote 5 and added endnote 6 ; table 1 ................ 4 changed digital input/ outpu t voltage to com parameter from ?0.3 v to +5.5 v to ?0.3 v to +5.3 v ............................................. 6 changes to smpl _ prd register definition section, table 24 , and avg_cnt register definition section ............................... 24 changes to table 31 ........................................................................ 28 4/13 rev. a to rev. b changes to table 2 ............................................................................ 5 updated outline dimensions ....................................................... 31 changes to ordering guide .......................................................... 31 5/06 rev. 0 to rev. a changes to figure 3 ........................................................................... 5 changes to figure 35 ...................................................................... 18 changes to status feedback section ............................................ 25 3/06 revision 0: initial version
data sheet ADIS16201 rev. c | page 3 of 32 specifications t a = ? 40 o c to + 125c, v dd = 3.3 v, tilt = 0 , unless otherwise noted. table 1 . parameter conditions min typ max unit inclinometer each axis input range operable to ~ 90 degree s 70 d egree s relative accuracy 15 degree s , 25c, max filter 0.25 d egree s 30 degree s , 25c, max filter 0.5 d egree s 60 degre e s , 25c, max filter 1.5 d egree s sensitivity 60 degree s , 25c 9.9 1 0 10.1 lsb/degree s sensitivity o ver temperature 30 degree s 50 ppm/c offset at 25c 2037 2048 2059 lsb offset o ver temperature 0.082 lsb /c accelerometer each axis input range 1 at 25c 1.7 g nonlinearity 1 % of full scale 0.5 2.5 % alignment error x sensor to y sensor 0. 1 d egree s cross axis sensitivity 2 % sensitivity at 25c 2.140 2.162 2.184 lsb/m g sensitivity o v er temperature 50 ppm/c offset at 25c , 0 g 8151 8192 8233 lsb offset o ver temperature 0.33 lsb /c accelerometer noise performance output noise at 25c, no averaging 22 lsb rms noise density at 25c, no averaging 0.37 lsb/hz rms accelerometer frequency response sensor bandwidth 2250 hz sensor resonant frequency 5.5 khz accelerometer self - test state 2 output change when active at 25c 372 708 1040 lsb temperature sensor output at 25c 1278 lsb scale factor ? 2.13 lsb/c adc input resolution 12 bits integral nonl inearity 2 lsb differential nonl inearity 1 lsb offset error 4 lsb gain error 2 lsb input range 0 2.5 v input capacitance during acquisition 20 p f on - chip voltage reference 2.5 v accuracy at 25 c ? 10 +10 mv reference temperature coefficient 40 ppm/ o c output impedance 70 ?
ADIS16201 data sheet rev. c | page 4 of 32 parameter conditions min typ max unit dac output 5 k ? / 100 pf to gnd resolution 12 bit s relative accuracy for code 101 to code 4095 4 lsb differential nonlinearity 1 lsb offset error 5 mv gain error 0.5 % output range 0 to 2.5 v output impedance 2 ? output settling time 10 s logic inputs input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v logic 1 input current, i in h v ih = v dd 0.2 1 a logic 0 input current, i in l v il = 0 v ? 40 ? 60 a input capacitance, c in 10 pf digital outputs output high voltage , v oh i source = 1.6 ma 2.4 v output low voltage , v ol i sink = 1.6 ma 0. 4 v s leep timer timeout period 3 0.5 128 sec onds flash memory endurance 4 2 0,000 cycles data retention 5 t j = 8 5c 2 0 years conversion rate minimum conversion time 244 s maximum conversion time 484 ms maximum throughput rate 4096 sps minimum throughput rate 2.066 sps power supply operating voltage range vdd 3.0 3.3 3.6 v power supply current normal mode, smpl_time 0x08 (f s 910 hz), at 25c 11 14 ma fast mode, smpl_time 0x07 (f s 1024 hz), at 2 5c 36 42 ma sleep m ode, at 25c 500 750 a turn - on time 6 130 m s 1 guaranteed by i mems packaged part testing , design, and/or characterization . 2 self - test response changes as the square of v dd . 3 guaranteed by d esign. 4 endurance is qualified as per jedec s tandard 2 2 method a117 and measured at ?40c, +25c, +85c, and +125c. 5 retention lifetime equivalent at junction temperature (t j ) 85c as per jedec standard 22 method a117. retention lifetime decreases with junction temperature. 6 the start - up time defines the t ime from vdd > 3.0 v to the fir st output register update. this parameter does not account for filter settling, which depend s on the smpl_prd and avg_cnt settings.
data sheet ADIS16201 rev. c | page 5 of 32 timing specifications t a = 25c, v dd = 3.3 v, tilt = 0, unless otherwise noted. table 2. parameter description min 1 typ max unit f sclk fast mode, smpl_time 0x07 (f s 1024 hz) 0.01 2.5 mhz normal mode, smpl_time 0x08 (f s 910 hz) 0.01 1.0 mhz t datarate chip select period, fast mode, smpl_time 0x07 (f s 1024 hz) 32 s t datarate chip select period, norm al mode, smpl_time 0x08 (f s 910 hz) 42 s t stall stall period, fast mode, smpl_prd 0x07 (f s 1024 hz) 10 s t stall stall period, normal mode, smpl_prd 0x08 (f s 910 hz) 12 s t cs chip select to clock edge 48.8 ns t dav data output valid after sclk edge 100 ns t dsu data input setup time before sclk rising edge 24.4 ns t dhd data input hold time after sclk rising edge 48.8 ns t df data output fall time 5 12.5 ns min t dr data output rise time 5 12.5 ns min t sfs cs high after sclk edge 5 ns typ 1 guaranteed by design, not tested. timing diagrams cs sclk t data rate t stall = t data rate ? 16/ f sclk t stall 05462-002 figure 2. spi chip select timing cs sclk dout din 1 2 3 4 5 6 15 16 w/r a5 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu 05462-003 figure 3. spi timing (utilizing spi settings typically identified as phase = 1, polarity = 1)
ADIS16201 data sheet rev. c | page 6 of 32 absolute maximum rat ings table 3 . parameter rating acceleration (any axis, unpowered) 3500 g acceleration (any axis, powered) 3500 g vdd to com ? 0.3 v to +7.0 v digital input/ output voltage to com ? 0.3 v to +5.3 v analog inputs to com ? 0.3 to vdd + 0.3 v analog inputs to com ? 0.3 to vdd + 0.3 v operating temperature range ? 40c to +12 5c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation o f the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4 . package characteristics package type ja jc device weight 1 6 - terminal lga 2 5 0c/w 25c/w 0. 6 grams esd caution
data sheet ADIS16201 rev. c | page 7 of 32 pin configuration an d function descripti ons aux adc vdd vref com nc aux com dio1 dio0 nc = no internal connection aux dac nc aux com rst sclk dout din x sensor y sensor or cs ADIS16201 bottom view (not to scale) 1 2 3 12 9 10 11 4 5 6 7 8 16 13 14 15 05462-004 figure 4. pin configuration table 5 . pin function descriptions pin no . mnemonic type 1 description 1 sclk i serial clock. sclk provides the serial clock for accessing data from the part and writing serial data to the control registers. 2 dout o data out. the data on this pin represents data being read from the control reg isters and is clocked out on the falling edge of the sclk. 3 din i data in. data written to the control registers is provided on this input and is clocked in on the rising edge of the sclk. 4 cs i chip select, active l ow. this inpu t frames the serial data transfer. 5, 6 d io0, dio1 i/o multifunction digital i/o p in s . 7, 11 nc C no connect. 8, 10 aux com s auxiliary grounds. connect to gnd for proper operation. 9 rst i reset, active l ow. this input resets t he embedded microcontroller to a known state. 12 aux dac o auxiliary dac analog voltage output. 13 vdd s + 3.3 v power supply. 14 aux adc i auxiliary adc analog input voltage. 15 vref o precision reference output. 16 com s common. reference point for a ll circuitry in the ADIS16201. 1 s = supply; o = o utput; i = input.
ADIS16201 data sheet rev. c | page 8 of 32 typical performance characteristics 2.144 2.9 3.7 power supply (v) acceleration sensitivity (lsb/mg) 2.174 2.170 2.165 2.161 2.157 2.153 2.148 3.0 3.1 3.2 3.3 3.4 3.5 3.6 05462-005 figure 5. acceleration sensitivity vs. power supply at 25c 25 0 ?150 150 (ppm/c) quantity 20 15 10 5 ?120 ?90 ?60 ?30 0 30 60 90 120 05462-006 figure 6. acceleration sensitivity tempco histogram at 3.3 v 2.132 ?60 140 temperature (c) acceleration sensitivity (lsb/mg) 2.192 2.183 2.175 2.166 2.158 2.149 2.141 ?40 ?20 0 20 40 60 80 100 120 05462-007 figure 7. acceleration sensitivity vs. temperature at 3.3 v 140 0 ?18 ?17 ?15 ?14 ?12 ?11 ?9 ?8 ?6 ?5 ?3 ?2 0 2 3 5 6 8 9 11 12 14 15 17 18 (mg) quantity 120 100 80 60 40 20 05462-008 figure 8. acceleration offset distribution at 25c/3.3 v/0 g 20 0 ?200 200 (ppm/c) quantity 18 16 14 12 10 8 6 4 2 ?160 ?120 ?80 ?40 0 40 80 120 160 05462-009 figure 9. acceleration offset tempco histogram at 3.3 v 50 ?50 2.9 3.7 power supply (v) acceleration offset (lsb) 40 30 20 10 0 ?10 ?20 ?30 ?40 3.0 3.1 3.2 3.3 3.4 3.5 3.6 05462-010 figure 10. acceleration offset vs. supply at 25c
data sheet ADIS16201 rev. c | page 9 of 32 90 0 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 (g) quantity 80 70 60 50 40 30 20 10 05462-011 figure 11 . x - axis self - test level at 25c/3.3 v 80 0 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 (g) quantity 70 60 50 40 30 20 10 05462-012 figure 12 . y - axis self - test level at 25c/3.3 v 1200 200 2.9 3.7 power supply (v) self-test shift (lsb) 1000 800 600 400 3.0 3.1 3.2 3.3 3.4 3.5 3.6 05462-013 figure 13 . self - test shift vs. supply at 25c 140 0 ?1.2 ?1.1 ?1.0 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 (degrees) quantity 120 100 80 60 40 20 05462-014 figure 14 . inclination offset distribution at 25c/3.3 v/0 g 20 0 ?200 200 (ppm/c) quantity 18 16 14 12 10 8 6 4 2 ?160 ?120 ?80 ?40 0 40 80 120 160 05462-015 figure 15 . inclination offset tempco histogram at 3.3 v 10 ?10 2.9 3.7 power supply (v) inclination offset (lsb) 3.0 3.1 3.2 3.3 3.4 3.5 3.6 8 6 4 2 0 ?2 ?4 ?6 ?8 05462-016 figure 16 . inclination offset vs. supply at 25c
ADIS16201 data sheet rev. c | page 10 of 32 150 0 607.6 607.8 608.0 608.2 608.4 608.6 608.8 609.0 609.2 609.4 609.6 609.8 610.0 610.2 610.4 610.6 610.8 611.0 611.2 611.4 611.6 611.8 612.0 612.2 612.4 (v/lsb) quantity 125 100 75 50 25 05462-017 figure 17 . adc gain distribution at 25c/3.3 v 80 0 ?2.4 ?2.1 ?1.8 ?1.5 ?1.2 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 (mv) quantity 70 60 50 40 30 20 10 05462-018 figure 18 . adc offset distribution at 25c/3.3 v 3 ?3 1 16381 adc state (lsb) 2 1 0 ?1 ?2 4096 8191 12286 05462-019 figure 19 . typical adc integral nonlinearity at 25c/3.3 v 3 ?3 1 16381 adc state (lsb) 2 1 0 ?1 ?2 4096 8191 12286 05462-020 figure 20 . typical adc differential nonlinearity 120 0 606.6 606.9 607.2 607.5 607.8 608.1 608.4 608.7 609.0 609.3 609.6 609.9 610.2 610.5 610.8 611.1 611.4 611.7 612.0 612.3 612.6 612.9 613.2 613.5 617.0 (v/lsb) quantity 100 80 60 40 20 05462-021 figure 21 . dac gain distribution at 25c/3.3 v 45 0 ?2.7 ?2.4 ?2.1 ?1.8 ?1.5 ?1.2 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.8 (mv) quantity 40 35 30 25 20 15 10 5 05462-022 figure 22 . dac offset distribution a t 25c/3.3 v
data sheet ADIS16201 rev. c | page 11 of 32 5 ?5 0 4096 dac state nonlinearity (lsb) 4 3 2 1 0 ?1 ?2 ?3 ?4 512 1024 1536 2048 2560 3072 3584 3 . 0 v / ?40 c 3 . 0 v / +25 c 3 . 0 v / +125 c 3 . 3 v / ?40 c 3 . 3 v / +25 c 3 . 3 v / +125 c 3 . 6 v / ?40 c 3 . 6 v / +25 c 3 . 6 v / +125 c 05462-023 figure 23 . typical dac integral nonlinearity 250 0 2.4975 2.4977 2.4979 2.4981 2.4983 2.4985 2.4987 2.4989 2.4991 2.4993 2.4995 2.4997 2.4999 2.5001 2.5003 2.5005 2.5007 2.5009 2.5011 2.5013 2.5015 2.5017 2.5019 2.5021 2.5023 (v) quantity 200 150 100 50 05462-024 fi g ure 24 . vref distribution at 25c/3.3 v 60 0 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 (c) quantity 50 40 30 20 10 05462-025 figure 25 . temperature distribution at 25 c/3.3 v 140 0 9.4 9.6 9.7 9.9 10.0 10.2 10.3 10.5 10.6 10.8 10.9 11.1 11.2 11.4 11.5 11.7 11.8 12.0 12.1 12.3 12.4 12.6 12.7 12.9 13.0 (ma) quantity 120 100 80 60 40 20 05462-026 figure 26 . normal mode power supply current distribution at 25c/3.3 v 140 0 29.0 29.6 30.2 30.8 31.4 32.0 32.6 33.2 33.8 34.4 35.0 35.6 36.2 36.8 37.4 38.0 38.6 39.2 39.8 40.4 41.0 41.6 42.2 42.8 43.4 (ma) quantity 120 100 80 60 40 20 05462-027 figure 27 . fast mode power supply current distribution at 25c/3.3 v 180 0 370 378 386 394 402 410 418 426 434 442 450 458 466 474 482 490 498 506 514 522 530 538 546 554 562 (a) quantity 160 140 120 100 80 60 40 20 05462-028 figure 28 . sleep mode power supply current dist ribution at 25c/3.3 v
ADIS16201 data sheet rev. c | page 12 of 32 0 ?50 150 temperature (c) sleep mode current (a) 0.0010 0.0008 0.0006 0.0004 0.0002 ?30 ?10 10 30 50 70 90 110 130 05462-029 figu r e 29 . sleep mode current vs. temperature at 3.3 v 0 2.9 3.7 supply voltage (v) sleep mode current (a) 0.0010 0.0008 0.0006 0.0004 0.0002 3.0 3.1 3.2 3.3 3.4 3.5 3.6 05462-030 figure 30 . sleep mode current vs. supply at 25c
data sheet ADIS16201 rev. c | page 13 of 32 t heory of operation the ADIS16201 is a complete dual - axis digita l inclinometer/ accelerometer that uses analog devices surface - micromachining process and embedded signal processing to make a functionally complete , low cost dual - axis sensor. the ADIS16201 offers a fully calibrated, dual C axis micro machined sensor elemen t that develops independent analog signals representative of the acceleration levels applied to the part. an on - b o ard precision adc samples t he acceleration signals, along with the power supply voltage, an internal temperature signal , and the auxiliary ana log input signal. these signals are then processed and latched into addressable output registers . the serial peripheral interface ( spi ) provides convenient, digital access to these registers . in addition, the acceleration signals are further processed to p roduce inc lination angle data for both axes . the inclination angle data rep resents the tilt away from the ideal plane , which in this cas e, is normal to the earths gravitational force. this calculation assumes that no force outside of the earths gravitati onal force is acting on the device. a ccelerometer o peration the acceleration sensor used in the ADIS16201 is a surface - machined, polysilicon structure built on top of a silicon wafer. polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. acceleration causes a d eflection in the differential capacitor structure that includes both fixed plates and plates that are attached to the moving mass. the fixed plates are driven by a set of square w aves that are 180 o out - of - phase from one another. acceleration deflect s the beam and unbalance s the differential capacitor, resulting in an output square wave whose amplitude is proportional to acceleration. phase sensitive demodulation techniques rectify the signal and determine the direction of the acceleration. the output of the demodulator is amplified, digitized, and processed to remove any process variations and sensitivities to supply variations. i nclinometer o peration the ADIS16201 inclinometer outp ut data is linear with respect to degrees of inclination and is dependent on no forces, other than gravity, acting on the device. the ADIS16201 leverages a simple geometrical relationship to convert its calibrated acceleration measurements into an accurate inclination angle estimate . figure 31 displays the acceleration measurements associated with each incline angle, along with the resulting inclination angle estimate produced by the ADIS16201. one important behavior to observe when using this approach is the fact that the relationship between the acceleration measurements and incl ination angle is nonlinear. this non - linear behavior results in larger quantization error changes as the inclination angle approaches 90 . figure 32 provides a closer look at this behavior by illustrating the increase in step size as the inclination angle estimate i ncreases. figure 33 offers a direct relationship between the quantization error and the overall inclination angle. 0 90.0 tilt (degrees) output 22.5 45.0 67.5 inclination acceleration 05462-031 figure 31 . acc eleration and inclination angle vs. actual tilt angle 75 90 tilt (degrees) output 80 85 inclination acceleration 05462-032 figure 32 . acceleration and inclination angle vs. actual tilt angle
ADIS16201 data sheet rev. c | page 14 of 32 1.5 ?1.5 0 90 tilt (degrees) error (degrees) 1.0 0.5 0 ?0.5 ?1.0 15 30 45 60 75 05462-033 figure 33 . inclination quantization error temperature sensor the temp_out control register allows the end user to monitor the internal temperature of the ADIS16201 to an accuracy of 5 c. the output data is presented in a straight binary format with a nominal 25 c d ie temperature correlating to a 1278 lsb read through the temp_out output data register. the temperature scale factor of ? 2.129 lsb/ c allows for a resolution of less than 0.5 c in the temperature reading within the output data register.
data sheet ADIS16201 rev. c | page 15 of 32 basic operation the ADIS16201 is designed for simple integration into indus- trial system designs, requiring only a 3.3 v power supply and a 4-wire, industry standard, serial peripheral interface (spi). registers that are accessed using the spi interface facilitate all of the input/output functions on the ADIS16201. each of these registers is assigned a unique address and data format tailored for its specific function. the spi port operates in a full duplex mode; data is clocked out of the dout pin at the same time command/address data is clocked in through the din pin. for more information on basic spi port operation, see the applications section. data output register access for the most basic operation of the ADIS16201, output data registers require only read commands for accessing calibrated sensor data, along with the temperature, power supply, and auxiliary analog input channel data. each read command requires two full 16-bit cycles. the first cycle is for transmitting the register address, and the second cycle is for reading the data. table 6 displays the appropriate bit map for the read command. bit a0 through bit a5 contain the address of the register being accessed. the appropriate sequencing for each spi signal ( cs , slck, din, and dout) during a read command can be found in figure 34. the data output register configuration is broken down into three different functions: new data ready bit (nd), alarm indicator (ea), and data bits (d0 to d13). the nd bit is used to determine if a particular register has been updated since the last read command. a logic level 1 for nd indicates that unread data is available. when a register is read, this bit is set to a 0 logic level. the alarm indicator provides users with a simple method for passively monitoring a variety of status/alarm conditions and can be used to simplify system-level processing requirements. the two acceleration output data registers are 14 bits in length and are formatted as twos complement binary numbers. the rest of the data output registers are 12 bits in length, leaving d12 and d13 as dont care bits. the output format for each of these registers, along with their addresses, can be found in table 7. each output data register has two different addresses. the first address is for the upper byte, which contains the most significant bits (d8 to d13), nd, and ea data. the second address is for the lower byte, which contains the eight least significant bits (d0 to d7). reading either of these addresses results in all 16 bits being clocked out on the dout line as defined in table 6 during the next spi cycle. address idle next command based on previous command 16-bit data word cs sclk din dout read bit = 0 zero 05462-034 figure 34. register read command sequence table 6. register read command bit map din w/ r 1 0 a5 a4 a3 a2 a1 a0 x x x x x x x x dout nd ea d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 upper byte lower byte 1 the w/ r bit is always 0 for read commands.
ADIS16201 data sheet rev. c | page 16 of 32 table 7 . data output register information name functi on address resolution ( b its) data format scale factor (per lsb) supply_out power supply data 0x 03, 0x 02 12 binary 1.22 mv xaccl_out x - axis acceleration data 0x 05, 0x 04 14 twos complement 0.4625 m g yaccl_out y - axis acceleration data 0x 07, 0x 06 14 twos complement 0.4625 m g aux_adc auxiliary analog input data 0x 09, 0x 08 12 binary 0.61 mv temp_out sensor temperature data 0x 0b, 0x 0a 12 binary ? 0.47 c xincl_out x - axis inclination data 0x 0d, 0x 0c 12 twos complement 0.1 yincl_out y - axis inclination data 0x 0f, 0x 0e 12 twos complement 0.1 table 8 . output coding example, xaccl_out 1, 2 acceleration level binary output hex output decimal +1.7 g 00 1110 0101 1011 0x0e5b 3675 +1 g 00 1000 0111 0010 0x0872 2162 +0.4625 g 00 0011 1110 1000 0x03e8 1000 +0.4625 m g 00 0000 0000 0001 0x0001 1 0 g 00 0000 0000 0000 0x0000 0 ? 0.4625 m g 11 1111 1111 1111 0x3fff ? 1 ? 0.4265 g 11 1100 0001 1000 0x3c18 ? 1000 ? 1 g 11 0111 1000 1110 0x378e ? 2162 ? 1.7 g 11 0001 1010 0101 0x31a5 ? 3675 1 two msbs have bee n masked off and are not considered in the coding . 2 nominal sensitivity (2.162 lsb/m g) and zero offset null performance are assumed .
data sheet ADIS16201 rev. c | page 17 of 32 p rogramming and control control register overview the ADIS16201 offers many programmable features that are controlled by writing commands to the appr opriate control registers using the spi. for added system flexibility and programmability, t he following sections describe these control s and specify the 28 digital control registers that are available using the spi interface. a high level listing of these registers is given within table 9 . the following sections expand upon the functionality of each of these control registers, providing for the full clarification of the behavior of each of the control registers. available control modes for the device include selectable sample rates for reading the seven output vectors, configurable output data, alarm setti ngs, control of the on - board 12 - bit auxiliary dac, handling of the two general - purpose i/o lines, facilitation of the sleep mode , enabling the self - test mode, and other miscellaneous control functions. the conversion process is repeated continually , providing for continuous update of the seven output registers. the n ew data ready bit (nd) flag s bits common to all seven output regis ters , allow ing the completion of the conversion process to be tracked via the spi. as an alternative, the digital i/o lines can be configured through software control to create a data - ready hardware function that can signal the completion of the conversion process. two independent alarms provide the ability to monitor any one of the seven output registers. they can be configured to report an alarm condition on either fixed thresholds or rates of change. the alarm conditions are monitored through the spi. in addition , the user can configure the digital i/o lines through software control to create an alarm function that allows for monitoring of the alarm conditions through hardware. the seven output signals noted above are calibrated independ - ently at the fact ory , delivering a high degree of accuracy. in addition, the user has access to independent offset and scale factors for each of the two acceleration and inclination output vectors. this allows independent scaling and level adjustment control of any one the se four registers prior to the values being read via the spi. in turn, field level calibrations can be implemented within the sensor itself using these offset and scale variables. system level commands provided within the sensor include automatic zeroing o f the four outputs using a single null command via the spi. in addition, the original factory calibration settings can be recovered at any point , using a simple factory reset command. control register acc ess the c ontrol registers within the adis 16201 are based upon a 16- bit / 2 - byte format , and they are accessed via the spi . the spi operates in full duplex mode with the data clocked out of the dout pin at the same time data is clocked in through the din pin. all commands written to the asis16201 are categor ized as write commands or read commands. all w rite commands are self - contained and take place within a single cycle . e ach r ead command requires two cycles to complete; t he first cycle is for transmitting the register address , and the second cycle is for re ading the data. during th e second cycle, when the d ata o ut line is active, the d ata i n line is used to receive the next sequentia l command. t his allows for overlapping the commands. for more information on basic spi port operation, see the applications s ection. the read and write commands are identified through the m ost s ignificant b it (msb), b15, of the received data. write a 1 to b15 to indicate a w rite command. write a 0 to b15 to indicate a r ead command. bit b13 through bit b8 contain the address of the control register that is being accessed. the remaining eight bits of the w rite command contain the data that is being written into the part , whereas the remaining eight bits of the r ead command contain dont care levels. given th at the data within the w rite command is eight bits in length, the 8 - bit data format is the default byte size. a w rite command operates on a single chip select cycle , as shown in figure 35 . the read command operates on a 2 - chip s elect cycle basis , as seen in figure 34. all 64 bytes of register space are accessed using the 6 - bit address. data written into the device is one byte at a time with the address of each byte being explicitly called out in the wr ite command. conversely, data being read from the device consists of two, back - to - back , 8 - bit variables being sent out , with the first byte out corresponding to the upper address (odd number address) and the second byte relating to the next lower address s pace (even number address). for example, a data read of a ddress 03h result s in the data from a ddress 03h being fed out followed by data from a ddress 02h. likewise, a data read of a ddress 02h result s in the same data stream being output from the device . the ADIS16201 is a flash - based device with the nonvolatile functional registers implemented as flash registers. take into account t he endurance limitation of 2 0,000 writes when considering the system - level integration of these devices . the n onv olatile column in table 9 indicates which registers are recovered upon power - up. the user must instigate a manual flash update command (using the command register ) in order to store the nonvolatile data registers , once they are configured proper ly . when performing a manual flash upda te command, the user needs to en sure that the power supply remains within limits for a minimum of 50 s after the write is initiated. this en sure s a successful write of the non volatile data.
ADIS16201 data sheet rev. c | page 18 of 32 table 9. control register mapping register name type nonvolatile address bytes function 0x00 to 0x01 2 reserved supply_out r 0x02 2 power supply output data xaccl_out r 0x04 2 x-axis acceleration output data yaccl_out r 0x06 2 y-axis acceleration output data aux_adc r 0x08 2 auxiliary adc data temp_out r 0x0a 2 temperature output data xincl_out r 0x0c 2 x-axis inclination output data yincl_out r 0x0e 2 y-axis inclination output data xaccl_ off r/w x 0x10 2 x-axis acceleration offset factor yaccl_ off r/w x 0x12 2 y-axis acceleration offset factor xaccl_ scale r/w x 0x14 2 x-axis acceleration scale factor yaccl_ scale r/w x 0x16 2 y-axis acceleration scale factor xincl_off r/w x 0x18 2 x-axis inclination offset factor yincl_ off r/w x 0x1a 2 y-axis inclination offset factor xincl_scale r/w x 0x1c 2 x-ax is inclination scale factor yincl_ scale r/w x 0x1e 2 y-axis inclination scale factor alm_mag1 r/w x 0x20 2 alarm 1 amplitude threshold alm_mag2 r/w x 0x22 2 alarm 2 amplitude threshold alm_smpl1 r/w x 0x24 2 alarm 1 sample period alm_smpl2 r/w x 0x26 2 alarm 2 sample period alm_ctrl r/w x 0x28 2 alarm source control register 0x2a to 0x2f 6 reserved aux_dac r/w 0x30 2 auxiliary dac data gpio_ctrl r/w 0x32 2 auxiliary digital i/o control register msc_ctrl r/w 0x34 2 miscellaneous control register smpl_prd r/w x 0x36 2 adc sample period control avg_cnt r/w x 0x38 2 defines number of sa mples used by moving average filter pwr_mde r/w 0x3a 2 counter used to determine length of power-down mode status r 0x3c 2 system status register command w 0x3e 2 system command register table 10. register write command bit map din w/r 0 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 upper byte lower byte address data cs s cl k din write bit = 1 zero 05462-035 figure 35. control register write command sequence of spi signals
data sheet ADIS16201 rev. c | page 19 of 32 control register d etails the control registers in th e ad is16201 are 16 bits in length. each of them has been assigned an address for their upper byte and lower byte. the bit map of each control register use s the numerical assignments that are displayed in the following table . msb lsb 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 th e upper byte consists of bit 8 to bit 15, and th e lower byte consists of bit 0 to bit 7. each of the follow ing sections provide s a description of each register that includes purpose, relevant scaling information, bit maps, address es , and default values. calibration the ADIS16201 outputs are pre calibrated at the factory, providing a high degree of accuracy and simpler system implementation. in addition, for system or field updates, the device has eight control registers associated w ith calibrating the acceleration and inclination output data (see the calibration register definitions section ) . each of these registers has read/write capability and is 16 bits (2 bytes) in length. all calibration registers are 12 bit s in length, with the exception of the i nclination o ffset registers, which are 9 bits in length. all data values are aligned to the lsb. the offset registers all utilize the twos complement format allowing for both positive and negative offsets. all scale registers utilize the straight binary format. the data within these eight calibration registers is utilized in offsetting and scaling of the output data registers according to the following relationship: ( ) c x a output + = where: x represents t he raw data prior to cali bration. c is the offset. a is the scalar. output represents the o utput d ata register where the resultant data is stored. all four inertial sensor outputs (x and y acceleration, x and y inclination) have their own independent set of calibration registers. simple access to these registers enables fi eld calibration to correct for in - system error sources. in particular, the offset control registers allow the user to reset to 0 / 0 m g reference point for the device. this is particularly important w hen considering the stack - up of the tolerances in mounting the ADIS16201 to a p rinted c ircuit b oard (pcb), the pcb to an enclosure, the enclosure mounted to the chassis of a piece of equipment, and so on . the result is that the ADIS16201 mechan ical reference can be offset several degrees from that of the end equipment mechanical reference , resulting in an accumulation of o ffset error s in the inclination and acceleration data output registers. t he offset registers provide a convenient tool for ma naging these types of errors. a global command is implemented within the ADIS16201 to simplify the loading of the offset s. once the end piece of equipment is leveled to its desired reference point , a null command can be sent to the ADIS16201 via the comman d control register , which zero s the two acceleration and the two inclination output data registers. this command loads all four offset registers with the inverse of their contents at the time of the null command. consequently, on the next reading of the se ven output data registers, the two acceleration and two inclination output data r egisters should be reset to mid - scale (neglecting noise and repeatability limitations). it is suggested that when the null command is implemented, the avg_cnt control register be set to 08h in order to maximize the filtering and reduce the effects of noise in determining the values to be loaded into the offset control registers. optionally , the user can manually load each of the eight calibration registers via the spi in order to calibrate the end system. this is applicable when the user plans to adjust the scale factors , thus requiring an external stimulus to excite the ADIS16201. calibration register definitions xaccl_ off register definition address scale 1 default format acce ss 0x11, 0x10 0.4624 mg 0x0000 twos complement r/w 1 scale is the weight of each lsb. the xaccl_off register is the user - controlled register for calibrating system - level acceleration offset errors. for the x - axis acceleration, it represents the c variab le in the calibration equation. the maximum calibration range is + 0.945 g , or +2047/ ? 2048 codes , assuming nominal sensor sensitivity. the contents of this register are nonvolatile . table 11. xaccl_off bit designations bit description 15:12 not used 11:0 d ata bits
ADIS16201 data sheet rev. c | page 20 of 32 xaccl_ scale register definition address scale 1 default format access 0x1 5 , 0x1 4 0.0 488 % 0x0 8 00 binary r/w 1 scale is the weight of each lsb. the xaccl_scale register is the user - controlled register for calibrating system - level acceleration sensitivity errors . for the x - axis a cceleration, it represe nts the a variable in the calibration equation. th is register offers a sensitivity calibration range of 0 to 2, or 0 to 4095 codes, assumi ng nominal sensor sensitivity. the co ntents of this register are non volatile. table 12. xaccl_ scale bit designations bit description 15:12 not used 11:0 data bits y accl_ off register definition address scale 1 default format r/w 0x1 3 , 0x1 2 0.4624 m g 0x0000 twos complement both 1 scale is the weight of each lsb. the yaccl_off register is the us er - controlled register for calibrating system - level acceleration offset errors. for the y - axis a cceleration, it represents the c variable in the calibration equation. the maximum calibration range is + 0.945 g , or +2047/ ? 2048 codes, assuming nominal sensor sensitivity. the contents of this register are nonvolatile. table 13. yaccl_off bit designations bit description 15:12 not used 11:0 data bits y accl_ scale register definition address scale 1 d efault format access 0x1 7 , 0x1 6 0.0 488 % 0x0 8 00 binary r/w 1 scale is the weight of each lsb. the yaccl_scale register is the user - controlled register for calibrating system - level acceleration sensitivity errors. for the y - axis a cceleration, it represen ts the a variable in the calibration equation. this register offers a sensitivity calibration range of 0 to 2, or 0 to 4095 codes, assuming nominal sensor sensitivity. the contents of this register a re non volatile. table 14. yaccl_s cale bit designations bit description 15:12 not used 11:0 data bits xincl_off register definition address scale 1 default format access 0x1 9 , 0x1 8 0. 1 0x0000 twos complement r/w 1 scale is the weight of each lsb. the xincl_off register is the user - controlled register for calibrating system - level inclination offset errors . for the x - axis inclination, it represents the c variabl e in the calibration equation. the maximum calibration range is + 25.5 or + 255/ ? 256 codes, assuming nominal sensor sensitivity. the contents of this register are nonvolatile. table 15. xincl_off bit designations bit description 15: 9 not used 8 :0 data bits x incl _ scale register definition address scale 1 defa ult format access 0x1d, 0x1c 0.0 488 % 0x0800 binary r/w 1 scale is the weight of each lsb. the xincl_scale register is the user - controlled register for calibrating system - level inclination sensitivity errors. for the x - axis inclination, it represents the a variable in the calibration equation. the calibration range is from 0 to 2, or 0 to 4095 codes, assuming nominal sensor sensitivity. the contents of this register are nonvolatile. table 16. xincl_scale bit designations bit descri ption 15:12 not used 11:0 data bits yincl_off register definition address scale 1 default format access 0x1b, 0x1a 0.1o 0x0000 twos complement r/w 1 scale is the weight of each lsb. the yincl_ off register is the user - controlled register for calibrati ng system - level inclination offset errors. for the y - axis inclination, it represents the c variable in the calibration equation. the maximum calibration range is + 25.5o or +255/ ? 256 codes, assuming nominal sensor sensitivity. the contents of this register are nonvolatile . table 17. yincl_off bit designations bit description 15:9 not used 8:0 data bits
data sheet ADIS16201 rev. c | page 21 of 32 yincl _ scale register definition address scale 1 defa ult format access 0x1f, 0x1e 0.0 488 % 0x0800 binary r/w 1 scale is the weight of each lsb. the yincl_scale register is the user - controlled register for calibrating system - level inclination sensitivity errors. for the y - axis inclination, it represents th e a variable in the calibration equation. the calibration range is from 0 to 2, or 0 to 4095 codes, assuming nominal sensor sensitivity. the co ntents of this register are non volatile. table 18. yincl_scale bit designations bit descr iption 15:12 not used 11:0 data bits alarm s the ADIS16201 contains two independent alarm functions that are referred to as alarm 1 and alarm 2. the alarm 1 function is managed by the alm_mag1 and alm_smpl1 control registers . t he alarm 2 function is mana ged by the alm_mag2 and alm_smpl2 control registers. both the alarm 1 and al arm 2 functions share the alm_c trl register. for simplicity, t he following text references the alarm 1 functionality only. the 16 - bit alm_c trl register serves three distinct roles in controlling the alarm 1 function. first , it is used to enable the overall alarm 1 function and select the output data variable that is to be monitored for the alarm condition. second , it is used to select whether the alarm 1 function is based upon a pre defined t hreshold (thr) level or a predefined r ate - o f - c hange (roc) slope. third, the alm_ctrl register can be use d in setting up one of the two g eneral - p urpose i nput/ o utput lines (gpio s ) to serve as a hardware output that indicates when an alarm condition has occurred. enabling the i/o alarm function, setting its polarity , and controlling its operation are accomplished using this register. note that when enabled, the hardware output indicator serves both the alarm 1 and alarm 2 functions and cannot be use d to differentiate between one alarm condition and the other. it is simply used to indicate that an alarm is active and that the user should poll the device via the spi to determine the source of the alarm condition (see the status register definition section ). because the alm_ctrl, msc_ctrl , and gpio_ctrl control registers can influence the same gpio pins, a priority level has been established to avoid conflicting assignments of the two gpio pins. this priority level is defined as msc_ctrl , which has precedence over alm_ctrl, which has precedence over gpio_ctrl. the alm_mag1 control register u sed in controlling the alarm 1 function has two roles . the first role is to store the value with which the output data variable is compared to discern if an alarm condition exists or not. the second role is to identify whether the alarm should be active for excursions above or below the alarm limit. if 1 is written to the gt1 bit of the alm_mag1 control register, the alarm is active for excurs ions extending above a given limit. if 0 is written to the gt1 bit, the alarm is active for excursions dropping below the given limit. the comparison value contained within the alm_mag1 control register is located within the lower 14 bits. the format util ized for this 14 - bit value should match that of the output data register that is being monitored for the alarm condition. for instance, if the yincl_out output data register is being mo nitored by alarm 1, then the 14 - bit value within the alm_mag1 control r egister take s on a twos complement format with each lsb equating to nominal 0.1 (assumes unity scale and zero offset factors). the alm_mag value is compared against the instantaneous value of the parameter being monitored. use caution when monitoring the temperature output register for the alarm conditions. here, the negative temperature scale factor results in the greater than and less than selections requiring reverse logic. when the thr function is enabled, the output data variable is compared against the alm_mag1 level. when the roc function is enabled, the comparison of the output data variable is against the alm_mag1 level averaged over the number of samples , as identified in the alm_smpl1 control register. this acts to create a comparison of ( units / time) or the derivative of the output data variable against a predefined slope.
ADIS16201 data sheet rev. c | page 22 of 32 the versatility built into the alarm function is intended to allow the user to adapt to a number of different applications. for example, in the case of monitoring a twos complement variable , the gt1 bit within the alm_mag1 control register can allow for the detection of negative excursions below a fixed level. in addition, the alarm 1 and alarm 2 functions can be set to monitor the same variable that allows the user t o discern if an output variable remains within a predefined window. other options include the roc function that can be used in monitoring high frequency shock levels in the acceleration outputs or slowly changing outputs in the inclination level over a pe riod of a minute or more. with the addition of the alarm hardware functionality, the ADIS16201 can be left to run independently of the main processor and interrupt the system only when an alarm condition occurs. conversely, the alarm condition can be monit ored through the routine polling of any one of the seven data output registers. note that the alarm functions work from instantaneous data and not averaged data that can be present when the avg_cnt register is not set to 0. the alarm hardware output indica tor is not latched but tracks the actual alarm conditions in real time. alm_mag1 register definition address default 1 format access 0x21, 0x20 0x0000 n/a r/w 1 default is valid only until the first register write cycle. the alm_mag1 register contain s th e threshold level for alarm 1. the contents of this register are nonvolatile. table 19. alm_mag1 bit designations bit description 15 greater t han a ctive a larm b it. 1: alarm is active for an output g reater t han alarm magnitude 1 reg ister setting. 0: alarm is active for an output l ess t han alarm magnitude 1 register setting. 14 not used . 13: 0 data bits. this number can be either twos complement or straight binary. the format is set by the value being monitored by this function. al m_smpl1 register definition address default 1 format access 0x25, 0x24 0x0000 binary r/w 1 default is valid only until the first register write cycle. the alm_smpl1 register contains the sample period information f or alarm 1, when it is set for rate - of - change alarm monitoring. the r ate - of - c hange alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the a lm_mag1 register. the co ntents of this register are non volatile. table 20. alm_smpl1 bit designations bit description 15:8 not used 7:0 data bit s alm_mag2 register definition address default 1 format access 0x23, 0x22 0x0000 n/a r/w 1 default is valid only until the first regi ster write cycle. the alm_mag2 register contains the threshold level for alarm 2. th e contents of this register are nonvolatile . table 21. alm_mag2 bit designations bit description 15 greater t han a ctive a larm b it. 1 : alarm is acti ve for an output g reater t han alarm magnitude 2 register setting. 0: alarm is active for an output l ess t han alarm magnitude 2 register setting. 14 not used . 13:0 data bits. this number can be either twos complement or straight binary. the format is set by the value being monitored by this function. alm_smpl2 register definition address default 1 format access 0x27, 0x26 0x0000 binary r/w 1 default is valid only until the first register write cycle. the alm_smpl2 register contains the sample period in formation f or alarm 2, when it is set for rate - of - change alarm monitoring. the r ate - of - c hange alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the al m_mag1 register. the co ntents of this register are non volatile. table 22. alm_smpl2 bit designations bit description 15:8 not used 7:0 data bits
data sheet ADIS16201 rev. c | page 2 3 of 32 alm_ctrl register definition address default 1 format access 0x29, 0x28 0x0000 n/a r/w 1 default is valid only until the first register write cycle. the alm_ctrl register contains the alarm control variables. table 23. alm_ctrl bit designations bit value description 15 rate of change (roc) enable for alarm 2 . 1: roc is active. 0: roc is inactive . 14:12 alarm 2 source selection . 000 alarm d isable . 001 alarm s ource: p ower s upply o utput . 010 alarm s our ce: x -a cceleration o utput . 011 alarm s our ce: y -a cceleration o utput . 100 alarm s ou rce: a uxiliary adc o u tput . 101 alarm s o urce: t emperature s ensor o utput . 110 alarm s ou rce: x -i nclination o utput . 111 alarm s ource: y -i nclination o utput . 11 rate of change (roc) enable for alarm 1 . 1: roc is active. 0: roc is inactive . 10:8 alarm 1 source selection . 000 alarm d isable . 001 alarm s ource: p ower s upply o utput . 010 alarm s our ce: x -a cceleration o utput . 011 alarm s our ce: y -a cceleration o utput . 100 alarm s ou rce: a uxiliary adc o utput . 101 alarm s o urce: t emperature s ensor o utput . 110 alarm s ou rce: x -i nclination o utput . 111 alarm s ource: y -i nclination o utput . 7:3 not used. 2 alarm output enable . 1: alarm output enabled . 0: alarm output disabled . 1 alarm output polarity . 1: active high . 0: active low . 0 alarm output line select . 1: dio1 . 0: d io0 . sample period contro l the seven output data variables within the ADIS16201 are sampled and updated at a rate based upon the smpl_prd control register. the sample period can be precisely controlled over more than a 3 - decade range using a time base with two settings and a 7 - bit binary count. the use of a time base that varies with a ratio o f 1:31 allows for a more optimal resolution in the sample period than a straight binary counter. this is reflected in figure 36 , where th e frequency is presented on a logarithmic scale. the choice of the two time base settings results in making the sample period setting more linear vs. the logarithmic frequency scale. note that the sample period given is defined as the cumulative time requi red to sample, process, and update all seven data output variables. the seven data output variables are sampled as a group and in unison with one another. whatever update rate is selected for one signal, all seven output data variables are updated at the s ame rate whether they are monitored via the spi or not. for a sample period setting of less than 1098.9 s (smpl_rate 0x07), the overall power dissipation in the part rises by approxi - mately 300% . the default setting for the smpl_rate register is 0x04 at initial power - up , thus allowing for the maximum spi clock rate of 2.5 mhz. 256 0 1 10k frequency (hz) smpl_prd value 192 128 64 10 100 1k 05462-036 figure 36 . smpl_prd values vs. sample frequency
ADIS16201 data sheet rev. c | page 24 of 32 smpl_prd register definition address default 1 format access 0x37, 0x36 0x000a n/a r/w 1 default is valid only until the first register write cycle. after using the manual flash update (command[3]), the data within this register is nonvolatile, allowing for data recovery upon reset. the initial value is set to 0x0a upon initial power- up, allowing for a sample period of ~744 s. table 24. smpl_prd bit descriptions bit description 15:8 not used. 7 adc time base control. 0: t b = 122.1 s 1: t b = 3.784 ms . 6:0 adc sample period control (n s ). relationship to the sample period control: t s = t b ( n s + 1) filtering control the ADIS16201 has the ability to perform basic filtering on the seven output data variables through the avg_cnt control register. the filtering performed is that of a low-pass, moving average filter. the size of the data being averaged (number of filter taps) is determined through the avg_cnt control register. the filtering applied through the avg_cnt control register is applied to all seven data output variables concurrently and, thus, one output variable cannot be filtered differently from another. the number of taps (n) within the moving average filter is calculated as cntavg n _ 2 ? where avg_cnt is shown as a decimal value. with avg_cnt set to 00h, n is reduced to 1, which effectively disables the moving average filter. at the other extreme, when avg_cnt is set to its maximum setting of 08h, n increases to 256, effectively reducing the apparent bandwidth by 256. note that the contribution from each tap is set to 1/(n) allowing for unity gain in the filter response. the frequency response of the moving average filter is given as: ) sin( ) sin( )( s s tfn tfn fh ?? ??? ? ? ? the more taps, the more poles, thus the steeper the slope of the roll-off. use caution with this filter mechanism because the amplitudes of the sideband peaks within the stop band are not reduced with an increasing number of taps, potentially allowing for high frequency components to leak through. sample frequency response plots for the moving average filter, utilizing various numbers of taps, are detailed in figure 37. 1.0 h( f ) ?0.5 00.5 f/fs frequency (hz) number of taps 0.5 0 0.1 0.2 0.3 0.4 n = 2 n = 4 n = 16 05462-037 figure 37. number of taps vs . sample frequency response avg_cnt register definition address default 1 format access 0x39, 0x38 0x0006 binary r/w 1 default is valid only until the first register write cycle. the avg_cnt register contains information that represents the number of averages to be applied to the output data. the number of averages can be calculated by powers of 2. for example, the default value of the register, 4, would result in 16 averages applied to the output data. the number of averages can be set to 1, 2, 4, 8, 16, 32, 64, 128, and 256. table 25. avg_cnt bit description bit description 15:4 not used 3:0 data bits (maximum = 1000, or a decimal value of 8) power-down control the ADIS16201 has the ability to power down for user-defined amounts of time, using the pwr_mde control register. the amount of time specified by the pwr_mde control register is equal to the binary count of the 8-bit control word multiplied by 0.5 seconds. therefore, the 255 codes cover an overall shutdown time period of 127.5 seconds. the pwr_mde register is volatile and is set to 0 upon both initial power-up and subsequent wake-ups from the power-down period. by setting the pwr_mde control register to a non-zero state, the ADIS16201 automatically powers down once the next sample period is completed and the seven data output registers are updated.
data sheet ADIS16201 rev. c | page 25 of 32 o nce the adi s16201 is placed into the power - down mode, it can only return to n ormal operation by timing out , a reset command (using the rst hardware control line ) , or by cycling the power applied to the part . once awake , the seven data output registers can be scanned to determine what the state of the output regist ers were prior to powering down. once the data is recovered , the device can be powered down again by writing a non - zero value to the pwr_mde control register and starting the process over. once the power - down time is complete, the recovery time for the adi s16201 is approximately 2 ms. this recovery time is implem ented within the device to allow for recovery of the adc prior to performing the next data conversion. note that the nd data bit within the seven data output control registers is cleared when the ad is16201 is powered down. likewise, the n ew d ata h ardware i/o line is placed into an inactive state prior to being powered down. the dac is placed into a power - down mode as well, which results in the dac output dropping to 0 v during the power - down period. all control register settings are retained while powered down with the exception of the pwr_mde control register , which is reset to 0 prior to power - down. pwr _ mde register definition address default 1 format access 0x3b, 0x3a 0x0000 binary r/w 1 default is valid only until the first register write cycle. the power - down period is determined by multiplying the binary value represented by the data bits times the constant 0.5 seconds . this results in a variable power - down period of 0.5 seconds to 12 7.5 second s with 0.5 seconds resolution in the setting . a setting of 0 disables the power - down m ode , whereas any non - zero entry place s the device in the power - down mode at the next update of the data output registers . the power - down register is volatile and is set t o all 0s upon initial power - up and recovery from the power - down mode. table 26 . pwr_mde bit descriptions bit description 15:8 not used 7:0 data bits status feedback the status control register within the ADIS16201 is utilized i n determining the present state of the device. the ability to monitor the device becomes necessary when and if the ADIS16201 has registered an alarm or error condition as indicated by the alarm enable (14) within the seven o utput data registers. the 16 - b it status register is broken into two bytes. the three lower bits of the lower data byte are used to indicate which error condition exists , while the two lower bits of the upper data byte are utilized in indicating which alarm condition exists. s tatus reg ister definition address default 1 format access 0x3 d , 0x3 c 0x0000 n/a read only 1 default is valid only until the first register write cycle. the s tatus control register contains the alarm/error flags that indicate abnormal operating conditions. see table 27 for each status bit definition. all flags are cleared upon the reading of the status register. the flags are set on a continuing basis as long as the error or alarm conditions persist. table 27. stat us bit descriptions b it d escription 15:10 not used . 9 alarm 2 status. 1: active 0: n ormal mode 8 alarm 1 status. 1: active 0: n ormal mode 7:4 not used . 3 spi c ommunications f ailure . 1: e rror condition 0: n ormal mode 2 control r egister u pdate f ail ed. 1: error condition 0: normal mode 1 power s upply a bove 3.625 v. 1: error condition 0 : n ormal mode 0 power s upply b elow 2.975 v. 1: e rror condi tion 0 : n ormal mode command control the command control register is utilized in sending global commands to the ADIS16201 device. there are four separate commands that act as global commands in the controlling of the ADIS16201 operation. any one of the four commands can be implemented by writing 1 to its corresponding bit location. the command control register h as write - only capability and is volatile. table 28 describes each of these global commands. command register definition address default 1 format access 0x 3f , 0x3 e 0x0000 n/a write only 1 default is valid only until the first re gister write cycle.
ADIS16201 data sheet rev. c | page 26 of 32 table 28. command bit descriptions bit description 15:8 not used . 7 software reset command . allows for resetting of the device via the spi . 6:4 not used . 3 manual flash update command. this command is utiliz ed in updating all of the nonvolatile registers to flash. once the command is initiated, the supply voltage, vdd, must remain within specified limits for 50 ms to assure proper update of the nonvolatile registers to flash. 2 auxiliary dac latch command . t his command acts to latch the a ux_ dac control register data into the auxiliary dac up on receipt of the command. this allows for sequential loading of the u pper and l ower aux_ dac d ata bytes via the spi without having the auxiliary dac transition into unwant ed , intermediate states based upon the individual aux_ dac data bytes. once the two bytes of aux_dac are loaded , the dac latch command is initiated to move the data into the auxiliary dac itself . 1 factory reset command . allows the user to reset all four s ystem level offset registers and all four system level scale registers to th e nominal settings (000h and 800h, respectively) upon receipt of command. data within the m oving a verage filters will likewise be reset. as the manual flash command identified belo w, this command stores all of the nonvolatile registers to flash. once the command is initiated , the supply voltage, vdd, must remain within specified limits for 50 ms to assure proper update of the nonvolatile registers to flash. 0 null command. loads th e x/y i nclination offset as well as the x/y a cceleration offset registers with values that zero out the inclinati o n and a cceleration outputs. useful as a single command to simultaneously zero both inclination and acceleration outputs. as the manual flash c ommand identified below, this command stores all of the nonvolatile registers to flash. once the command is initiated, the supply voltage, vdd, must remain within specified limits for 50 ms to assure proper update of the nonvolatile registers to flash. mi scellaneous control register the m sc_ctrl control register within the ADIS16201 provides control of two miscellaneous functions : the d ata - r eady h ardware i/o function and the s elf - t est function. the bits to control these two functions are shown in table 29. the operation of the d ata - r eady hardware i/o function is very similar to the a larm hardware i/o function (controlled through the alm_ctrl control register). in this case, the m sc_cntrl register can be used in setting up one of th e two gpio pins to serve as the hardware output pin that indicates when the sampling, conversion , and processing of the seven data output variables has been completed. this register provides the ability to enable the data - r eady hardware function and establ ish its polarity. the d ata - r eady hardware i/o pin is reset automatically to an inactive state part way through the next conversion cycle , resulting in a pulse train with a duty cycle varying from ~15 % to 35% , depending upon the sample period setting. upon completion of the next sample/conversion/processing cycle, the d ata r eady hardware i/o line is reasserted. t he msc_ctrl, alm_ctrl , and gpio_ctrl control registers can influence the same gpio pins . a priority level has been established to avoid conflicting assignments of the two gpio pins. this priority level is defined as msc_ctrl and has precedence over alm_ctrl , which has precedence over gpio_ctrl. the s elf - t est e nable bit allows the user to place the ADIS16201 into a diagnostics mode for purposes of ver ifying the base sensor s operation. when this bit is set high, an electrostatic force is generated internal ly to the sensor. the resulting movement within the sensor allows the end user to test if the accelerometer is functional. typical change in the outp ut is 328 m g (corresponding to 708 lsb). once the s elf - t est enable bit is returned to a low state, normal operation is resumed. msc_ctrl register definition address default 1 format access 0x35, 0x34 0x0000 n/a r/w 1 default is valid only until the first register write cycle. the 16 - bit m iscellaneous c ontrol register is used in the controlling of the s elf - t est and d ata - r eady hardware functions. this includes turning on and off the s elf - test function , as well as enabling and configuring the d ata - r eady func tion. for the d ata - r eady function , the written values are nonvolatile , allowing for data recovery upon reset. the s elf - t est d ata is volatile and is set to 0s upon reset. this register has r ead/ w rite capability. table 29 . msc_ctrl bi t descriptions bit description 15:9 not used . 8 self - t est e nable. 1: st enabled 0 : st disabled 7:3 not used . 2 data -r eady e nable. 1: dr enabled 0 : dr disabled 1 data -r eady p olarity. 1 : active high 0: a ctive low 0 data -r eady line s elect. 1: dio1 0: di o0
data sheet ADIS16201 rev. c | page 27 of 32 p eripherals auxiliary adc functi on the auxiliary adc function integrates a standard 12 - bit adc into the ADIS16201 to digitize other system - level analog signals. the output of the adc can be monitored through the aux_adc c ontrol register, as defined in table 6 and table 7 . the adc consists of a 12 - bit successive approximation converter. the output data is presented in straight binary format , with the full scale range extending from 0 v to vref. a hig h precision, low drift, factory - calibrated 2.5 v reference is also provided. figure 38 shows the equivalent circuit of the analog input structure of the adc. the input capacitor, c1, is typically 4 pf and can be attributed to parasitic package capacitance. the two diodes provide esd protection for the analog input. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this would cause these diodes to become forward - biased and start conducting. they can handle 10 ma without causing irreversible damage to the part. the resistor is a lumped component that represents the on resistance of the switches. the value of this resistance is typically 100 . c apacitor c2 represents the adc sampling capacitor and is typically 16 p f. c2 c1 r1 vdd d d 05462-038 figure 38 . equivalent analog input circuit conversion phase: switch open track phase: switch closed for ac applications, removing high frequency compon ents from the analog input signal is recommended through the use of an rc low - pass filter on the relevant analog input pins. in applications where harmonic distortion and signal - to - noise ratio are critical, the analog input should be driven from a low imp edance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. when no input amplifier is used to drive the analog input, the source impedance should be limited to value s lower than 1 k. the maximum source impedance depend s on the amount of total harmonic distortion (thd) that can be tolerated. auxiliary dac functi on the auxiliary dac fu nction integrates a standard 12 - bit dac into the ADIS16201 . t he dac output is buffe red and fed off - chip to allow for the control of miscellaneous system - level functions. data is downloaded through the writing of two adjacent data bytes , as defined in its register definition . t o prevent the dac from transitioning through inadvertent state s during data downloads, a single command is used to simultaneously latch both data bytes into the dac after they have been written into the aux_dac control register. this command is implemented by writing 1 to b it 2 of the command control register , which , once received, result s in the dac output transitioning to the desired state. the dac output provides an output range of 0 v to 2.5 v. t h e dac output buffer features a true rail - to - rail output stage. this means that, unloaded, the output is capable of rea ching within 5 mv of ground. moreover, the dacs linearity performance (when driving a 5 k resistive load to ground) is good through the full transfer function, except for c ode 0 to c ode 100. linearity degradation near ground is caused by saturation of the output amplifier. as the output is forced to sink more current, the nonlinear region at the bottom of the transfer function becomes larger. l arger current demands can significantly limit output voltage swing. aux_dac register definition address default 1 format access 0x31, 0x30 0x0000 binary r/w 1 default is valid only until the first reg ister write cycle. the aux_ dac register control s the ADIS16201s dac function. the data bits provide a 12- bit binary format number with 0 representing 0 v and 0x0fffh representing 2.5 v. the data within this regis ter is volatile and is set to 0s upon reset . this register has r ead/ w rite capability. table 30 . aux_dac b it descriptions bit description 15:12 not used 11:0 data bits
ADIS16201 data sheet rev. c | page 28 of 32 general purpose i/o control as previously noted, the ADIS16201 provides two general - p urpose, bi directio nal i/o pins (gpio s) that are available to the user for control of auxiliary circuits within the target application . all i/o pins are 5 v tolerant , meaning that the gpios support an input voltage of 5 v. all gpio pins hav e an internal pull - up resistor of a pproximately 100 k , and their drive capability is 1.6 ma. the direction, as well as the logic level , can be controlled for these gpio pins through the gpio_ctrl control register, as defined in table 31. these same gpio pins are also controllable through the alm_ctrl and msc_ctrl control registers. the priority for these three control registers in controlling the two gpio pins is msc_ctrl has precedence over alm_ctrl , which has precedence over gpio_ctrl. gpio_ctrl register defini tion address default 1 format access 0x33, 0x32 0x0000 n/a r/w 1 default is valid only until the first register write cycle. auxiliary digital i/o control register. the data within this register is volatile and is set to 0 s upon reset. table 31 . gpio_ctrl bit descriptions bit description 15:10 not used . 9 general - purpose i/o line 1 polarity. 0: low 1: high 8 general - purpose i/o line 0 polarity. 0: low 1: high 7:2 not used. 1 general - purpose i/o line 1 , data direction contro l. 0: input 1: output 0 general - purpose i/o line 0 , data direction control. 0: input 1: output
data sheet ADIS16201 rev. c | page 29 of 32 applications serial peripheral interface (spi) the ADIS16201 integrates a hardware spi on-chip. spi is an industry-standard synchronous serial interface that allows data to be transmitted and received simultaneously, that is, full duplex up to a maximum bit rate of 2.5 mbps depending upon the sample period selection. the spi port is configured for slave operation and consists of four pins. dout the data out pin (dout) is an output pin used to transmit data out of the ADIS16201. the data is transmitted in a 16-bit (2Cbyte) format, msb first. din the data-in pin (din) is an input pin that is used for the reception of data from the master. the data is received in a 16-bit (2-byte) format with the w/ r control bit and address contained in the first data byte and the data contained within the second data byte, msb first. sclk the serial clock pin (sclk) is used to synchronize the data being transmitted and received through the sclk period. therefore, a 16-bit (2-byte) word is transmitted/received after 16 sclk periods. the sclk pin is configured as an input. cs in the ADIS16201 a transfer is initiated by the assertion of the chip select pin ( cs ), which is an active-low signal. the spi port then transmits and receives data in 16-bit blocks until the transfer is concluded by de-assertion of cs . the control registers within the ADIS16201 are based upon a 16-bit (2-byte) format. data is loaded in from the din pin of the ADIS16201 on the rising edge of sclk. this requires 16 serial clocks for every data transfer framed by the low period of the cs line. the part operates in full duplex mode with the data clocked out of the dout pin, likewise on the rising edge of the sclk. for each read command received, the corresponding output data is clocked out of the dout pin during the following cycle, as defined by the cs line. output response figure 39 displays the typical output response for the ADIS16201 for several gravitational measurement orientations. this is a convenient plot for understanding the basic orientation of the inertial sensor measurement axes. bottom view (not to scale) 1 1 1 1 x _accl out = 0lsb y _accl out = ?2162lsb notes 1. data shown in twos complement format. x_accl out = 0lsb y_accl out = +2162lsb x _accl out = ?2162lsb y_accl out = 0lsb x_accl out = +2162lsb y_accl out = 0lsb earth?s surface 05462-039 figure 39. output resp onse vs. orientation hardware considerations the ADIS16201 can be operated from a single 3.3 v (3.0 v to 3.6 v) power supply. the ADIS16201 integrates two decoupling capacitors that are 1 f and 0.1 f in value. for the local operation of the ADIS16201, no additional power supply decoupling capacitance is required. however, if the system power supply presents a substantial amount of noise, additional filtering can be required. if additional capacitors are required, connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, note that all analog and digital grounds should be referenced to the same system ground reference point. grounding and board layout recomendations maintaining low impedance signal return paths can be very critical in managing system-level noise effects. for best results, use a single, continuous ground plane that is tied to each ADIS16201 ground pin via short via and trace lengths. in addition to maintaining a low-impedance ground structure, routing the spi signals away from any sensitive analog circuits, such as the adc and dacs (if they are in use), can help mitigate system-level noise risks.
ADIS16201 data sheet rev. c | page 30 of 32 bandgap reference the ADIS16201 provide s an on - chip band gap reference of 2.5 v, which is utilized by the on - board adc and dac. this internal reference also appears on the v ref pin. this reference can be connected to external circuits in the system. an external buffer would be required because of the low drive capability of the vref output. power - on reset operation an internal power - on r eset (por) is implemented interna ll y to the ad i s16201. for v dd below 2.35 v, the internal por hold s the ADIS16201 in reset. as v dd rises above 2.35 v, a n intern al timer time s out for typically 130 ms before the part is released from reset. the user must ensure that the power supply has reached a stable 3.0 v minimum level by this time. likewise , on power - down, the internal por hold s the ADIS16201 in reset until v dd has dropped below 2.35 v. figure 40 illustrates the operation of the internal por in detail. vdd p or 130 m s t y p 2 . 35 v t y p 05462-040 figure 40 . internal power - o n reset operation second - level assembly the adis16 201 can be attached to the s econd - level assembly board using sn63 (or equivalent) or lead - free solder. figure 41 and table 32 provide acceptable solder reflow profiles for each solder type. note: these profiles may not be the opti mum profile for the users application. in no case should 260c be exceeded. it is recommended that the user develop a reflow profile based upon the specific application. in general, keep in mind that the lowest peak temperature and shortest dwell time abo ve the melt temperature of the solder result in less shock and stress to the product. in addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly. 05462-042 t p t l t 25c to peak t s preheat critical zone t l to t p temperature time ramp-down ramp-up t smin t smax t p t l figure 41 . acceptable solder reflow profi les table 32. condition profile feature sn63/pb37 pb - f r ee average ramp rate (t l to t p ) 3c/sec max 3c/sec max preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time (t smin to t smax ) (t s ) 60 sec to 120 sec 60 sec to 150 sec t smax to t l ramp - up rate 3c/sec 3c/sec time maintained above liquidous (t l ) liquidous temperature (t l ) 183c 217c time (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240c + 0c/ C 5c 2 60c + 0c/ C 5c time within 5c of actual peak temperature (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp - down rate 6c/sec max 6c/sec max time 25c to peak temperature 6 min max 8 min max example pad layout 1.178 bsc (8 plcs) 0.500 bsc (16 plcs) 1.127 bsc (16 plcs) 0.670 bsc (12 plcs) 7.873 bsc (2 plcs) 05462-041 figure 42 . examp le pad layout
data sheet ADIS16201 rev. c | page 31 of 32 o utline dimensions 121409-c s i d e v i e w t o p v i e w b o t t o m v i e w pin 1 indica t or 1.000 bsc (16) 3.90 max 1 4 5 8 9 1 2 1 3 1 6 5.391 bsc (4) 2.6955 bsc (8) 5.00 typ 8.373 bsc (2) 0.200 min (all sides ) 0.797 bsc (12 ) 0.373 bsc (16) 9.35 9.20 sq 9.05 figure 43 . 16 - terminal stacked land grid array [ lga ] (cc - 16 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADIS16201ccc z ?40c to +125 c 16- terminal stacked land grid a rray [ lga ] cc -16-2 ADIS16201/pcb evaluation board 1 z = rohs compliant part.
ADIS16201 data sheet rev. c | page 32 of 32 notes ? 2006 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05462 - 0 - 8/13(c)

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